Implementation of Global History Branch Prediction Using MicroBlaze Processor
AbstractIn this paper, using VHDL (Very high speed IC Hardware Description Language) hardware modeling the complete design of a 32-bit MIPS (Microprocessor without Interlocked Pipeline Stages) MicroBlaze processor is presented. The MIPS and top level is designed using (Xilinx vivado Design Suite 2018.1) program. Dynamic branch predictors are common because it can be achieve accurate results in branch prediction without change sequence execution instruction, in order to improve accuracy in branch desired, proposed new active (design ) conditional branch predictor by connected with MicroBlaze processor and select number of entry that appropriate for these techniques by using bimodal dynamic branch predictor. A procedure that performs bimodal executed and the results are discussed this technique provides better prediction accuracy but require more power and complexity increases exponentially in design.
J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 5th ed., San Francisco, USA: Morgan Kaufmann, 2012.
S. P. Dandamudi, Fundamental of computer organization and design, Computer Science, 1th ed., New York, Springer, September 22, 2002.
Di Wu, K. Aasaraai, and A. Moshovos, “Low-cost, high-performance branch predictors for soft processors”, in2013 23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, Sept 2013.
L. Chen, S. Dropsho, and D. H. Albonesi, “Dynamic data dependence tracking and its application to branch prediction”, in High-Performance Computer Architecture, 2003. IEEE, Anaheim, CA, USA, 2003.
R.Thomas , M.Franklin, C.Wilkerson, J.Stark, “ Improving branch prediction by dynamic data flow-based identification of correlated branches from a large global history ”, in Proceedings of the 30th annual international symposium on Computer architecture, vol. 31, no. 2, pp. 257-266, May 2003.
C. Egan, “Dynamic Branch Prediction in High Performance Super Scalar Processors”, Ph. D. thesis, University of Hertfordshire, August 2000.
S. Sechrest, C.-C. Lee, and T.N. Mudge. “Correlation and aliasing in dynamic branch predictors”. In Proceedings of the 23rd International Symposium on Computer Architecture, Vol. 24, no. 2, pp.22-32, May 1996.
E. Sprangle, R.S. Chappell, M. Alsup, and Y. N. Patt. “The Agree predictor: A mechanism for reducing negative branch history interference”, on conference Proceedings the 24th Annual International Symposium on Computer Architecture , Denver, Colorado, USA, June 1997.
D. L. Perry, VHDL: Programming by Example, 4th ed., America: McGraw-Hill, 2002.
C.-C. Lee, C.C. Chen, and T.N. Mudge. “The bi-mode branch predictor”. On conference Proceedings of the 30th Annual International Symposium on Microarchitecture, Research Triangle Park, NC, USA, November 1997.
Juan, L.A., et al., “Confidence Estimation for Branch Prediction Reversal”, in Proceedings of the 8th International Conference on High Performance Computing. Spain, 2001.
M.Abd-El-Barr and Hesham El-Rewini, “Fundamentals of computer organization and architecture”. New Jersey, USA: John Wiley& Sons, 2005.
S. S. Omran and I. A. Amory, “Design and Implementation of Resizable Cache Memory using FPGA”. The second international Engineering Conference IEC, Ishik University, Irbil, Iraq, 2016.
K. P. Singh, S. Parmar, “Vhdl Implementation of a MIPS-32 Pipeline Processor”, International Journal of Applied Engineering Research, vol. 7, No.11, pp. 1952-1956, 2012.
J. L. Hennessy and D. A. Patterson, “Computer Organization and Design: The Hardware/Software Interface”, 4th Waltham, USA: Morgan Kaufmann, 2012.
T.Olga, Steve, Chris and Rachel, “Ultra Low Power Cooperative Branch Prediction”, Ph. D .Philosophy, Institute of Computing Systems Architecture, University of Edinburgh, 2015.
J.W. Kwak, C.S Jhon, “High-performance embedded branch predictor by combining branch direction history and global branch history,” in Proc. IET Computers & Digital Techniques, vol.2, no.2, pp.142-154, March 2008.
H. Arora, S. Kotecha, R. Samyal, “Dynamic Branch Prediction Modeller for RISC Architecture,” in Proc. International Conference Machine Intelligence and Research Advancement (ICMIRA), pp.397-401, Dec. 21-23,2013.
J. P. Shen, M. H. Lipasti, Modern processor design fundamentals of superscalar processors, USA, Waveland Press, 2005.
N. Panwar, M. Kaur, G. Singh, “Performance Analysis of Branch Prediction Unit for Pipelined Processors”, International Journal of Computer Applications, Vol. 128, no.16,pp.975-8887, October 2015.
J. E. Smith. “A study of branch prediction strategies ”, In Proceedings of the 8th Annual International Symposium on Computer Architecture,vol.21,no.1, pp. 135-148, May 1981.
S. McFarling, “Combining Branch Predictors”, TN-36, Digital Western Research Laboratory, June1993.
T. Ball, and R.L. James, “ Branch prediction for free”, In Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation, New York, USA June 1993.
Xilinx Inc. Micro Blaze Processor Reference Guide, July 2012.
Xilinx Inc. 7 Series FPGAs Overview, Feb.
Authors who submit papers with this journal agree to the following terms:
- Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
- Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
- Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See The Effect of Open Access).
- By submitting the processing fee, it is understood that the author has agreed to our terms and conditions which may change from time to time without any notice.
- It should be clear for authors that the Editor In Chief is responsible for the final decision about the submitted papers; have the right to accept\reject any paper. The Editor In Chief will choose any option from the following to review the submitted papers:A. send the paper to two reviewers, if the results were negative by one reviewer and positive by the other one; then the editor may send the paper for third reviewer or he take immediately the final decision by accepting\rejecting the paper. The Editor In Chief will ask the selected reviewers to present the results within 7 working days, if they were unable to complete the review within the agreed period then the editor have the right to resend the papers for new reviewers using the same procedure. If the Editor In Chief was not able to find suitable reviewers for certain papers then he have the right to accept\reject the paper.B. sends the paper to a selected editorial board member(s). C. the Editor In Chief himself evaluates the paper.
- Author will take the responsibility what so ever if any copyright infringement or any other violation of any law is done by publishing the research work by the author
- Before publishing, author must check whether this journal is accepted by his employer, or any authority he intends to submit his research work. we will not be responsible in this matter.
- If at any time, due to any legal reason, if the journal stops accepting manuscripts or could not publish already accepted manuscripts, we will have the right to cancel all or any one of the manuscripts without any compensation or returning back any kind of processing cost.
- The cost covered in the publication fees is only for online publication of a single manuscript.