Novel Machine Learning Approach for Defect Detection in DFT Processes

Abstract

Recent advances in semiconductor technology have highlighted significant challenges in effectively testing modern integrated circuits (ICs). As device densities increase and defect mechanisms become more diverse, conventional Design for Testability (DFT) methodologies – while indispensable – must contend with exponential growth in test complexity. This paper reviews the essential DFT practices, including scan-based structures, boundary scan, and built-in self-test (BIST), and examines how these practices address a variety of logical fault models. It further explores machine learning (ML) techniques as valuable tools for enhancing defect detection and diagnosis. By leveraging classification algorithms such as support vector machines and neural networks, ML-driven approaches can reduce test pattern generation time, improve bridging-fault coverage, and streamline board- or wafer-level screening. Collectively, this paper underscores how strategic synergy between DFT and ML can raise fault coverage, improve diagnostic precision, and contain testing costs in the face of ongoing technology scaling.