1.
Aladwany M, Alsaegh Z. Architectural Design and Implementation of Bit Error Rate Tester on FPGA. ASRJETS-Journal [Internet]. 2016 Jul. 5 [cited 2024 May 3];21(1):178-93. Available from: https://asrjetsjournal.org/index.php/American_Scientific_Journal/article/view/1839