ALADWANY, M.; ALSAEGH, Z. Architectural Design and Implementation of Bit Error Rate Tester on FPGA. American Scientific Research Journal for Engineering, Technology, and Sciences, [S. l.], v. 21, n. 1, p. 178–193, 2016. Disponível em: https://asrjetsjournal.org/index.php/American_Scientific_Journal/article/view/1839. Acesso em: 4 may. 2024.