Aladwany, Mann, and Zahraa Alsaegh. “Architectural Design and Implementation of Bit Error Rate Tester on FPGA”. American Scientific Research Journal for Engineering, Technology, and Sciences 21, no. 1 (July 5, 2016): 178–193. Accessed September 17, 2025. https://asrjetsjournal.org/American_Scientific_Journal/article/view/1839.