Aladwany, M. and Alsaegh, Z. (2016) “Architectural Design and Implementation of Bit Error Rate Tester on FPGA”, American Scientific Research Journal for Engineering, Technology, and Sciences, 21(1), pp. 178–193. Available at: https://asrjetsjournal.org/American_Scientific_Journal/article/view/1839 (Accessed: 17 September 2025).