Performance Study of Strain Engineered CMOS Inverter Logic Using Silicon Nanowire and Carbon Nanotube Field Effect Transistors

Authors

  • Imtiaj Khan Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology, Dhaka-1000, Bangladesh
  • Ovishek Morshed Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology, Dhaka-1000, Bangladesh
  • Sharif Mohammad Mominuzzaman Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology, Dhaka-1000, Bangladesh

Keywords:

inverter, strain, transconductance, direct tunneling, velocity saturation.

Abstract

Various non-ballistic effects have significant impacts on the characteristics of nanoscale devices whose performance can be boosted by strain engineering. The effects of uniaxial compressive and tensile strains on Complementary Metal-Oxide-Semiconductor (CMOS) inverter circuits consisting of Silicon Nanowire Field-Effect-Transistor (SiNW-FET) and Carbon Nanotube Field-Effect-Transistor (CNT-FET) have been investigated in this paper. At first, a CMOS inverter circuit has been developed using single-walled CNT-FET and SiNW-FET. A comparative analysis of the transconductances of both types of devices along with their dependence on applied strain has been presented. Afterwards, Simmons direct tunneling effect has been observed for both strained and unstrained CNT-FETs. Simulation result signifies that strained CNT-FET inverter has lower gate leakage current than its unstrained counterpart. Finally, a comparison between the effects of strains on the velocity vs electric field characteristics for both SiNW-FET and CNT-FET has been studied. As switching delay time for a CMOS inverter circuit is related to the velocity saturation effect, a conclusion can be drawn from these curves that for SiNW-FET CMOS inverter, tensile strain increases the switching delay time whereas compressive strain decreases it for high applied field. Accordingly, for CNT-FET CMOS inverter, strain increases the switching delay time for specific chirality.

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Published

2017-10-22

How to Cite

Khan, I., Morshed, O., & Mominuzzaman, S. M. (2017). Performance Study of Strain Engineered CMOS Inverter Logic Using Silicon Nanowire and Carbon Nanotube Field Effect Transistors. American Scientific Research Journal for Engineering, Technology, and Sciences, 37(1), 99–109. Retrieved from https://asrjetsjournal.org/index.php/American_Scientific_Journal/article/view/3371

Issue

Vol. 37 No. 1 (2017)

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Articles

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